Re: [Iverilog-devel] Unbounded vectors as parameters in SV functions

[Stephen W. <st...@ic...>]

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The good news here is that the latest Icarus Verilog does support
dynamic arrays, so what you propose should work. There may be
details of the implementation that does not work yet, just let
me know and I'll try to tackle the missing bits.

The example output that you propose does use dynamic arrays, so
should work. If it does not, I can address that.

On 10/29/2014 06:03 AM, Maciej Sumiński wrote:
> Hi,
> 
> I evaluated the previously proposed solution and none of them is 
> feasible at the moment.
> 
> I rejected support for unbounded vectors in SV as I felt I could
> not do that in a clean and reliable way. Aside from that, it is
> not compliant with the standard, so it should be avoided if
> possible.
> 
> Function instancing will not work in at least one case. The
> problem appears when someone tries to call a function that takes
> unbounded std_logic_vector and passes as an argument a function
> that returns unbounded std_logic_vector:
> 
> --------- function strange_fun(inp : std_logic_vector) return
> std_logic_vector is begin -- body end function;
> 
> result <= strange_fun(strange_fun(B"1110")); ---------
> 
> In the above example, it is not possible to say what is the size
> of the vector returned by the nested call, until the runtime. vvp 
> instruction set expects vector boundaries to be given as
> constants, therefore it is not possible to express the above code
> with available instructions.
> 
> If instead of packed arrays we could use unpacked arrays, then
> dynamic arrays are suitable for the task. Fortunately, it is also
> possible to perform bit-stream casting between packed and unpacked
> arrays (including the dynamic type). That way vectors of unknown
> size can be casted to dynamic arrays as needed.
> 
> In the attachment you may find code examples that illustrate the
> way I would like to follow. It is still a bit twisted, but I think
> this is the simplest method. Please let me know if you notice any
> flaws.
> 
> The implementation will require support for type casting in 
> SystemVerilog. That is the first part I would like to code unless 
> there are objections.
> 
> Regards, Orson
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)

iEYEARECAAYFAlRVWOQACgkQrPt1Sc2b3iljbwCggnooxsbJg9Nd9mEkGA25PjFg
wykAoOtpbTHKkr7iaMx/mDYv5Gze9fLh
=QjmI
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