[Iverilog-devel] Expression concatenation in VHDL

[Maciej S. <mac...@ce...>]

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Hi,

Branch that supports expression concatenation in VHDL is ready to be
merged [1] together with tests [2]. There is also support for VHDL's
integer() function.

I have investigated further the problem of range boundaries evaluation.
The problem with the following example code is a bit deeper.

- --------------
function test_func(word_i : std_logic_vector)
return std_logic_vector is
	for I in word_i'range loop
		-- do sth
	end loop;
end function;
- --------------

It is not only about exact evaluation of range boundaries. As far as I
know, SystemVerilog does not allow to declare functions that take and
return vectors (i.e. packed arrays) of undefined size. There are dynamic
arrays, but they are valid only for unpacked dimensions.

Currently I see two possible solutions, one on ivl side and another in
vhdlpp:

* Support for unconstrained vectors in ivl

It does not solve the problem of determining the direction of for-loops
that use the 'range attribute, so the previously proposed solution would
have to be applied.
This would have to be explicitly enabled using a flag, so by default ivl
conforms to the IEEE standard.
Just to be clear, I do not ask anyone to implement it. If that is the
right method then it is a perfect opportunity for me to dive deeper into
ivl code.

* Create extra function instances with name mangling in vhdlpp

During the elaboration step the type of parameters for a particular
function call could be determined and used to create a copy of the
function that works with specific constrained types. For example:

- --------------
function test_func(word_i : std_logic_vector)
return std_logic_vector is
	-- function body
end function;
- --------------

could be instantiated as:

- --------------
function slv7_0__test_func__slv7_0(word_i : std_logic_vector(7 downto 0))
return std_logic_vector(7 downto 0) is
	-- function body
end function;

function slv1_4__test_func__slv1_4(word_i : std_logic_vector(1 to 4))
return std_logic_vector(1 to 4) is
	-- function body
end function;
- --------------

in case it is called with the presented argument types.

In VHDL functions that return unconstrained std_logic_vector are allowed
to return vectors of different sizes every time. Example:

- --------------
function func(sel : std_logic) return std_logic_vector is
begin
  if sel = '1' then
    return "001100";
  else
    return "111";
  end if;
end function;
- --------------

This can solved thanks to strong typing, so you could deduce the
returned type by looking up the assignment left hand's type.

I am not sure yet which one is the way to go, but maybe you already see
that one of them is wrong and could be rejected.

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/47
2. https://github.com/orsonmmz/ivtest/tree/concat_test
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