Re: [Iverilog-devel] New VHDL attributes

[Maciej S. <mac...@ce...>]

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I have overlooked one important thing about ranges. There are cases
when one cannot evaluate array boundaries until the run-time. An
example is a function that takes std_logic_vector without specifying
its size, e.g.

function test_func(word_i : std_logic_vector)
return std_logic_vector is
	for I in word_i'range loop
		-- do sth
	end loop;
end function;

Because std_logic_vector may have indices increasing or decreasing (to
vs downto), the 'range attribute has to determine appropriate for-loop
condition and afterthought.
It would be easy to apply SystemVerilog's foreach here, but there is
no counterpart for 'reverse_range.
There is another solution that comes to my head:

for(i = $left(word_i), bool _rising = $left(word_i) < $right(word_i);
	_rising ? i <= $right(word_i) : i >= $right(word_i);
	i = i + (_rising ? 1 : -1))

It determines the right iteration direction during the run-time, but I
am not sure if that is the most elegant solution. Maybe someone else
knows what else could be applied to solve the problem.

Regards,
Orson

On 10/10/2014 07:03 PM, Maciej Sumiński wrote:
> Hi Steve,
> 
> There is a branch [1] that adds support for VHDL attributes:
> 'range, 'reverse_range, 'left & 'right. There are also tests for
> the mentioned features [2].
> 
> Before you merge the changes, I would like to attract your
> attention to two things that I might have potentially got wrong:
> 
> * patch for continuous assignment of 2-state nets (commit 1a4edca) 
> Previously VHDL 'integer' was translated to 'bool[31:0]', but as
> we agreed I have changed that to 'int'. I did so, because the
> attributes could not correctly recognize boundaries for arrays of
> integers ('left returned 31, 'right returned 0, no matter what was
> the actual size of the array). This caused some problems with vvp
> that had to simulate code containing continuous assignments for
> 2-state nets. I patched vvp to allow this, but I am not sure if it
> solves the problem right way.
> 
> * 'reverse_range (commit c7beef9) As 'range' is an official VHDL
> reserved keyword, it was easy to write a bison rule that recognizes
> the attribute. I was not sure how should I deal with
> 'reverse_range', so for the moment I added it to the gperf 
> dictionary. Intuitively I find it wrong, but I had no other idea
> how to solve it.
> 
> If anyone has a better idea for the above issues, I am all ears.
> 
> I am almost done with support for expressions concatenation, so you
> may expect it soon. I would have written this message a bit
> earlier, but I really did not know if the vvp patch is acceptable.
> 
> Regards, Orson
> 
> 1. https://github.com/steveicarus/iverilog/pull/46 2.
> https://github.com/orsonmmz/ivtest/tree/range_test
> 
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