Re: [Iverilog-devel] Variables in subprograms

[Cary R. <cy...@ya...>]

Hi Orson,

On the surface translation to LLVM IR seems simple, but when you start considering all the extra support needed for the VPI interface, delays, scheduling, etc. it is a much bigger task. It may still be beneficial. To me this turns into an effort like SystemC where there is a large library that needs to be implemented that would allow the base LLVM IR to be used for implementing the code that looks like a normal programming language. Also don't forget that Verilog requires four state variables in the context of normal expressions, etc.

I was actually thinking about this the other day from a CPU architecture point of view. Specifically if we have a standard well thought out instruction set then we could possibly use LLVM, C++, etc. as the micro architecture to implement the base instruction set. Using a standard instruction set may also allow us to synthesize to real hardware all or part of the simulator to generate hardware speedup of the simulation. I think of this like the Java processors for the JVM. The VPI interface or more specifically the system tasks and functions that use the VPI interface in their implementation complicate synthesis significantly. The current vvp interface is like this for procedural code, but the rest of the implementation uses different concepts (e.g. gates, continuous assignments, etc.).


Cary



On Wednesday, October 1, 2014 8:55 AM, Maciej Sumiński <mac...@ce...> wrote:
 


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Hi Steve,

Support for variables in VHDL subprograms is already done [1], together
with suitable tests [2].

Now I would like to take care of 'range and 'reverse_range attributes.
I think these should be easily translatable using $left & $right
system functions. For example:

- ---------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity range_test is
  port (inp : in std_logic_vector(8 downto 4);
        outp : out std_logic_vector(8 downto 4));
end range_test;

architecture test of range_test is
begin
  process(inp) begin
    for i in inp'range loop
        outp(i) <= not inp(i);
    end loop;
  end process;
end test;
- ---------------------------------------------

could be converted to:

- ---------------------------------------------
module range_test(input wire logic[8:4] inp,
                  output logic[8:4] outp);
always @(inp) begin
  longint i;
  for (i = $left(inp); i >= $right(inp); i = i - 1) begin
    outp[i] <= ~(inp[i]);
  end
end
endmodule
- ---------------------------------------------

There is also one thing that kept me pondering recently. I am not that
familiar with vvp principles, but it seems that its assembly-like code
format could be translated to the LLVM Intermediate Representation [3].
It is just a general idea, but maybe ivl could output the LLVM IR that
could be interpreted by llvm together with some kind of simulator runtime.
Has anyone else considered it? Do you already see any obstacles that
would made the task impossibly hard?

Regards,
Orson

[1] https://github.com/steveicarus/iverilog/pull/45
[2] https://github.com/orsonmmz/ivtest/tree/subprogram_test
[3] https://idea.popcount.org/2013-07-24-ir-is-better-than-assembly/
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