Re: [Iverilog-devel] Variables in subprograms

[Stephen W. <st...@ic...>]

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On 10/01/2014 08:55 AM, Maciej Sumiński wrote:
> Now I would like to take care of 'range and 'reverse_range
> attributes. I think these should be easily translatable using $left
> & $right system functions. For example:

Yes, although you can also use "foreach" loops. For example,
translate "for i in inp'range" to "foreach (inp[i])" to get
a more direct match. The foreach loop support was added to
Icarus Verilog a month or two ago.

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Steve Williams                "The woods are lovely, dark and deep.
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