Re: [Iverilog-devel] Another set of SystemVerilog sanity checks

[Iztok J. <izt...@gm...>]

$ irun sv_foreach1.sv
irun: 14.10-s003: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
ncsim> run
FAILED -- foo[0][7] == xxxxx
Simulation complete via $finish(1) at time 0 FS + 0
./sv_foreach1.sv:41     $finish;
ncsim> exit



$ irun sv_foreach2.sv
irun: 14.10-s003: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
ncsim> run
ncsim: *E,TRNULLID: NULL pointer dereference.
          File: ./sv_foreach2.sv, line = 52, pos = 8
         Scope: main
          Time: 0 FS + 0
./sv_foreach2.sv:52      if (foo[ia][ib].a !== ia[1:0] || foo[ia][ib].b !==
ib[2:0]) begin
ncsim> exit




$ irun sv_foreach3.sv
irun: 14.10-s003: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_foreach3.sv
         for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
                 |
ncvlog: *E,UNDIDN (sv_foreach3.sv,65|10): 'idx1': undeclared identifier
[12.5(IEEE)].
         for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
                            |
ncvlog: *E,UNDIDN (sv_foreach3.sv,65|21): 'idx1': undeclared identifier
[12.5(IEEE)].
         for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
                                       |
ncvlog: *E,UNDIDN (sv_foreach3.sv,65|32): 'idx1': undeclared identifier
[12.5(IEEE)].
         for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
                                              |
ncvlog: *E,UNDIDN (sv_foreach3.sv,65|39): 'idx1': undeclared identifier
[12.5(IEEE)].
            for (idx2 = 0 ; idx2 < 7 ; idx2 = idx2+1)
                    |
ncvlog: *E,UNDIDN (sv_foreach3.sv,66|13): 'idx2': undeclared identifier
[12.5(IEEE)].
            for (idx2 = 0 ; idx2 < 7 ; idx2 = idx2+1)
                               |
ncvlog: *E,UNDIDN (sv_foreach3.sv,66|24): 'idx2': undeclared identifier
[12.5(IEEE)].
            for (idx2 = 0 ; idx2 < 7 ; idx2 = idx2+1)
                                          |
ncvlog: *E,UNDIDN (sv_foreach3.sv,66|35): 'idx2': undeclared identifier
[12.5(IEEE)].
            for (idx2 = 0 ; idx2 < 7 ; idx2 = idx2+1)
                                                 |
ncvlog: *E,UNDIDN (sv_foreach3.sv,66|42): 'idx2': undeclared identifier
[12.5(IEEE)].
              if (foo[idx1][idx2] != null) begin
                         |
ncvlog: *E,UNDIDN (sv_foreach3.sv,67|18): 'idx1': undeclared identifier
[12.5(IEEE)].
              if (foo[idx1][idx2] != null) begin
                               |
ncvlog: *E,UNDIDN (sv_foreach3.sv,67|24): 'idx2': undeclared identifier
[12.5(IEEE)].
        module worklib.main:sv
                errors: 10, warnings: 0
ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
irun: *E,VLGERR: An error occurred during parsing.  Review the log file for
errors with the code *E and fix those identified problems to proceed.
 Exiting with code (status 2).




$ irun sv_queue3.sv
irun: 14.10-s003: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit