Re: [Iverilog-devel] Another set of SystemVerilog sanity checks

[Stephen W. <st...@ic...>]

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You know what? That's working out pretty well. Thanks!

On 08/25/2014 11:18 AM, Victor Lyuboslavsky wrote:
> FYI. Riviera-PRO and ModelSim are available on
> www.EDAPlayground.com <http://www.EDAPlayground.com> so we could do
> some sanity checking there. They're not Big-2, but should give some
> preliminary data :)
> 
> For example, sv_foreach1.sv <http://sv_foreach1.sv> results are at 
> http://www.edaplayground.com/x/XLr # KERNEL: FAILED -- foo[0][7] ==
> xxxxx
> 
> -Victor
> 
> 
> On Mon, Aug 25, 2014 at 12:14 PM, Stephen Williams
> <st...@ic... <mailto:st...@ic...>> wrote:
> 
> 
> Hi folks,
> 
> I'm working on some more complex issues of foreach loops and queue
> assignments, and I would once again like to get a sanity check of
> the attached programs to make sure I properly understand the tested
> behaviors.
> 
> Can someone with access to Big-N SV tools try the attached
> examples?
> 
> Thanks!
> 
> 
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- -- 
Steve Williams                "The woods are lovely, dark and deep.
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