Re: [Iverilog-devel] Another set of SystemVerilog sanity checks

[Victor L. <vi...@vi...>]

FYI. Riviera-PRO and ModelSim are available on www.EDAPlayground.com so we
could do some sanity checking there.
They're not Big-2, but should give some preliminary data :)

For example, sv_foreach1.sv results are at
http://www.edaplayground.com/x/XLr
# KERNEL: FAILED -- foo[0][7] == xxxxx

-Victor


On Mon, Aug 25, 2014 at 12:14 PM, Stephen Williams <st...@ic...> wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
> Hi folks,
>
> I'm working on some more complex issues of foreach loops and
> queue assignments, and I would once again like to get a sanity
> check of the attached programs to make sure I properly understand
> the tested behaviors.
>
> Can someone with access to Big-N SV tools try the attached examples?
>
> Thanks!
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
>
> iEYEARECAAYFAlP7bwEACgkQrPt1Sc2b3ikTmACeJ4cjvLLgHE3q8zZISQXDu+CI
> ZVwAoJBL5L8UChFVLLaJ7RD7ou+4Xmy5
> =UiBB
> -----END PGP SIGNATURE-----
>
>
> ------------------------------------------------------------------------------
> Slashdot TV.
> Video for Nerds.  Stuff that matters.
> http://tv.slashdot.org/
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>