Re: [Iverilog-devel] Some delay code to test

[Evan L. <sa2...@cy...>]

What are you actually seeing? Presumably CVC is showing 1 on both ca and 
gt at time 1? If so, that would be pretty hard to justify.

11.6.1 is definitive on continuous assignments at time 0 - the 
'continuous assignment process' is evaluated at time 0, and an active 
update event is added to the event queue. On the other hand, I'm pretty 
sure that this was not actually specified prior to 2005, so it would be 
interesting to see what XL does. I'd be very surprised if XL got this 
'wrong', though - continuous assignments were always meant to model 
combinatorial logic correctly, unlike always blocks, and you can't 
initialise correctly by ignoring the delays.

For initialisation of the gate output, 2005/page 112 explicitly shows 
this case. For 'buf #3 g2 (q, qi)', the diagram shows q unknown till 
time 3. This diagram also appears in the OVI V1 LRM from 1991 (Figure 
'7-1: Module schematic and the simulation times of initial value 
propagation'), so no excuses there.