Re: [Iverilog-devel] using -s to define top module gets error

[Lonnie G. <lg...@sr...>]

It is top_sim



On Aug 13, 2014, at 11:32 AM, Iztok Jeras <izt...@gm...> wrote:

> Just in case, did you check the module name inside top_sim.v is it top_sim or is it different?
> 
> 
> On 13 August 2014 18:28, Lonnie L Gliem <lg...@sr...> wrote:
> So I changed it to just the name of the file top_sim.v
> 
> error: Unable to find the root module "top_sim" in the Verilog source.
>      : Perhaps ``-s top_sim.v'' is incorrect?
> 1 error(s) during elaboration.
> 
> Then I tried just top_sim
> 
> error: Unable to find the root module "top_sim" in the Verilog source.
>      : Perhaps ``-s top_sim'' is incorrect?
> 1 error(s) during elaboration.
> 
> 
> 
> On Wed, 2014-08-13 at 09:23 -0700, Stephen Williams wrote:
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA1
> >
> >
> > The "-s" takes the module name, not the path to the source file
> > that contains the module.
> >
> > On 08/13/2014 09:11 AM, Lonnie L Gliem wrote:
> > > I am having trouble in a simulation where it finds way too many
> > > top
> > >
> > > modules. So I tried using the -s option to tell it which one is the
> > > top.
> > >
> > >
> > >
> > > But I get this error.
> > >
> > >
> > >
> > > error: Unable to find the root module
> > > "/export/home/lgliem/libs/libsim/ulogic_sim/top_sim.v" in the
> > > Verilog
> > >
> > > source.
> > >
> > > : Perhaps ``-s
> > > /export/home/lgliem/libs/libsim/ulogic_sim/top_sim.v'' is
> > > incorrect?
> > >
> > > 1 error(s) during elaboration.
> > >
> > >
> > >
> > > The module is there so I am not sure what is wrong.
> > >
> > >
> > >
> > > Lonnie
> > >
> > >
> > >
> > >
> > >
> > > ------------------------------------------------------------------------------
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> > - --
> > Steve Williams                "The woods are lovely, dark and deep.
> > steve at icarus.com           But I have promises to keep,
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