[Iverilog-devel] system verilog syntax error.

[Lonnie G. <lg...@sr...>]

I tried the latest snapshot:
Icarus Verilog version 0.10.0 (devel) (s20130827)

I get the following errors from this code in an altera system verilog
file. 

Lonnie

/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: error:
malformed statement
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: error:
malformed statement
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: error:
malformed statement
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: error:
malformed statement
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: error:
malformed statement

altera .sv file

//--------------------------------------------------------------------------
// Function Name    : strtobits
// Description      : takes in a string where
// each character represents a hexadecimal number, transforms that number into
// 4-bits, concatenates the result and returns it.
//--------------------------------------------------------------------------

function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits;
	input [8*MEM_INIT_STRING_LENGTH : 1] my_string;
	begin

        integer char_idx;  line 1361
	integer bit_idx;        1362
	reg[7:0] my_char;       1363
	reg[3:0] hex_value;     1364
	reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;