Re: [Iverilog-devel] Some SystemVerilog tests

[Iztok J. <izt...@gm...>]

$ irun sv_queue1.sv
irun: 12.10-p001: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
file: sv_queue1.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x1eeb5f29>
            streams:   1, words: 14566
    Loading native compiled code:     .................... Done
    Building instance specific data structures.
    Design hierarchy summary:
                 Instances  Unique
        Modules:         1       1
        Registers:       4       4
        Initial blocks:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV12.10.003/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit