Re: [Iverilog-devel] Some SystemVerilog tests

[Stephen W. <st...@ic...>]

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Gaah! Made the changes, but didn't save them out. Try this:


On 07/24/2014 08:43 AM, Iztok Jeras wrote:
> Hi Stephen,
> 
> It seems you have sent the same file as before, there are the same 
> errors around the !== operator:
> 
> file: sv_queue1.sv <http://sv_queue1.sv> if (words[0] !== "Hello")
> begin | ncvlog: *E,BDSTLO (sv_queue1.sv
> <http://sv_queue1.sv>,17|14): Illegal type string left operand to
> !== (case inequality) operator [SystemVerilog]. if (words[0] !==
> "Hello") begin | ncvlog: *E,TYCMPAT (sv_queue1.sv
> <http://sv_queue1.sv>,17|29): !== (case inequality) operator types
> are not equivalent (expecting datatype compatible with 'string' but
> found 'packed array [39:0] of logic' instead).
> 
> Regards, Iztok Jeras
> 
> 
> On 24 July 2014 17:35, Stephen Williams <st...@ic... 
> <mailto:st...@ic...>> wrote:
> 
> 
> Thanks for the debugging effort. It's amazing how these corner 
> cases can really throw one for a loop.
> 
> In any case, I've attached an improved version of sv_queueu1.sv 
> <http://sv_queueu1.sv>, that should address the issues you
> discovered.
> 
> On 07/24/2014 01:21 AM, Iztok Jeras wrote:
>> Hi,
> 
>> I have been debugging it for a bit, and I found out "Hello" is
>> of type logic[39:0] and not string, as you might expect. The
>> standard 1800-2012 seems to specify this on the bottom of page
>> 40. One way to let the test pass is to use the != operator
>> instead of !==. It is also possible to force the type of the
>> string literal with string'("Hello").
> 
>> Here is some code checking the types, and its output:
> 
>> $display(words[0]); $display(words[1]); 
>> $display($typename(words)); $display($typename(words[0])); 
>> $display($typename("Hello")); 
>> $display($typename(string'("Hello")));
> 
>> Hello World string$[$] string logic[39:0] string
> 
>> So as I mentioned changing the operator to != works, but casting 
>> to string does not. This might be a bug in the simulator since 
>> allowed data types for the !== operator are "Any except real and 
>> shortreal" (standard page 220).
> 
>> if (words[0] !== string'("Hello")) begin | ncvlog: *E,BDSTLO 
>> (sv_queue1.sv <http://sv_queue1.sv>
>> <http://sv_queue1.sv>,26|14):
> Illegal type string
>> left operand to !== (case inequality) operator [SystemVerilog].
>> if (words[0] !== string'("Hello")) begin | ncvlog: *E,BDSTRO 
>> (sv_queue1.sv <http://sv_queue1.sv>
>> <http://sv_queue1.sv>,26|30):
> Illegal type string
>> right operand to !== (case inequality) operator [SystemVerilog].
> 
> 
>> So I replaced the operators and rerun the example, now I get:
> 
>> $ irun sv_queue1.sv <http://sv_queue1.sv> <http://sv_queue1.sv>
> irun: 14.10-p001: (c)
>> Copyright 1995-2014 Cadence Design Systems, Inc. Recompiling... 
>> reason: file './sv_queue1.sv <http://sv_queue1.sv>
> <http://sv_queue1.sv>' is newer than
>> expected. expected: Thu Jul 24 10:13:31 2014 actual:   Thu Jul
>> 24 10:14:57 2014 file: sv_queue1.sv <http://sv_queue1.sv>
> <http://sv_queue1.sv> module
>> worklib.main:sv errors: 0, warnings: 0 Caching library 'worklib' 
>> ....... Done Elaborating the design hierarchy: Top level design 
>> units: main Building instance overlay tables:
>> .................... Done Generating native compiled code:
>> worklib.main:sv <0x58e06083> streams:   1, words: 11050 Building
>> instance specific data structures. Loading native compiled code:
>> .................... Done Design hierarchy summary: Instances
>> Unique Modules:         1 1 Registers:       4       4 Initial
>> blocks:  1       1 Writing initial simulation snapshot:
>> worklib.main:sv ncsim: *W,ONEOPT: Only one -USELICENSE option
>> allowed, using the first one (IESXL:DEFAULT).
> 
>> Running simulation with license features associated with
>> mnemonic 'IESXL'... Incisive_Enterprise_Simulator 14.10, 1 copy
>> - Successful Loading snapshot worklib.main:sv
>> .................... Done ncsim> source 
>> /tools/opt/cadence/INCISIV14.10.001/tools/inca/files/ncsimrc
>> ncsim> run FAILED -- nums[0] = 1 Simulation complete via
>> $finish(1) at time 0 FS + 0 ./sv_queue1.sv:70
>> <http://sv_queue1.sv:70>
> <http://sv_queue1.sv:70>
>> $finish; ncsim> exit
> 
>> The second example is passing after replacing the operators.
> 
>> $ irun sv_queue2.sv <http://sv_queue2.sv> <http://sv_queue2.sv>
> irun: 14.10-p001: (c)
>> Copyright 1995-2014 Cadence Design Systems, Inc. file:
> sv_queue2.sv <http://sv_queue2.sv>
>> <http://sv_queue2.sv> module worklib.main:sv errors: 0,
>> warnings: 0 Caching library 'worklib' ....... Done Elaborating
>> the design hierarchy: Top level design units: main Building
>> instance overlay tables: .................... Done Generating
>> native compiled code: worklib.main:sv <0x597c2a14> streams:   1,
>> words:  5243 Building instance specific data structures. Loading
>> native compiled code: .................... Done Design hierarchy
>> summary: Instances Unique Modules:         1       1 Registers:
>> 4       4 Initial blocks:  1       1 Writing initial simulation
>> snapshot: worklib.main:sv ncsim: *W,ONEOPT: Only one -USELICENSE
>> option allowed, using the first one (IESXL:DEFAULT).
> 
>> Running simulation with license features associated with
>> mnemonic 'IESXL'... Incisive_Enterprise_Simulator 14.10, 1 copy
>> - Successful Loading snapshot worklib.main:sv
>> .................... Done ncsim> source 
>> /tools/opt/cadence/INCISIV14.10.001/tools/inca/files/ncsimrc
>> ncsim> run PASSED ncsim: *W,RNQUIE: Simulation is complete.
>> ncsim> exit
> 
> 
>> The modified examples are attached.
> 
>> Regards, Iztok Jeras
> 
> 
> 
>> On Thu, Jul 24, 2014 at 9:40 AM, Iztok Jeras 
>> <izt...@gm... <mailto:izt...@gm...>
> <mailto:izt...@gm... <mailto:izt...@gm...>>>
> wrote:
> 
>> Hi Stephen,
> 
>> First I tried compiling without any changes and I got errors. I 
>> will try to find the issue.
> 
>> irun sv_queue1.sv <http://sv_queue1.sv> <http://sv_queue1.sv>
> irun: 14.10-p001: (c)
>> Copyright 1995-2014 Cadence Design Systems, Inc. file:
> sv_queue1.sv <http://sv_queue1.sv>
>> <http://sv_queue1.sv> if (words[0] !== "Hello") begin | ncvlog: 
>> *E,BDSTLO (sv_queue1.sv <http://sv_queue1.sv>
> <http://sv_queue1.sv>,17|14): Illegal type
>> string left operand to !== (case inequality) operator 
>> [SystemVerilog]. if (words[0] !== "Hello") begin | ncvlog: 
>> *E,TYCMPAT (sv_queue1.sv <http://sv_queue1.sv>
> <http://sv_queue1.sv>,17|29): !== (case
>> inequality) operator types are not equivalent (expecting
>> datatype compatible with 'string' but found 'packed array [39:0]
>> of logic' instead). if (words[$] !== "World") begin | ncvlog:
>> *E,BDSTLO (sv_queue1.sv <http://sv_queue1.sv>
>> <http://sv_queue1.sv>,22|14):
> Illegal type string
>> left operand to !== (case inequality) operator [SystemVerilog].
>> if (words[$] !== "World") begin | ncvlog: *E,TYCMPAT
>> (sv_queue1.sv
> <http://sv_queue1.sv>
>> <http://sv_queue1.sv>,22|29): !== (case inequality) operator
>> types are not equivalent (expecting datatype compatible with
>> 'string' but found 'packed array [39:0] of logic' instead). if
>> (tmp_word !== "Hello") begin | ncvlog: *E,BDSTLO (sv_queue1.sv
>> <http://sv_queue1.sv> <http://sv_queue1.sv>,28|17): Illegal type
>> string left operand to !== (case inequality) operator
>> [SystemVerilog]. if (tmp_word !== "Hello") begin | ncvlog:
>> *E,TYCMPAT (sv_queue1.sv
> <http://sv_queue1.sv>
>> <http://sv_queue1.sv>,28|29): !== (case inequality) operator
>> types are not equivalent (expecting datatype compatible with
>> 'string' but found 'packed array [39:0] of logic' instead). if
>> (words[0] !== words[$]) begin | ncvlog: *E,BDSTLO (sv_queue1.sv
> <http://sv_queue1.sv>
>> <http://sv_queue1.sv>,33|14): Illegal type string left operand
>> to !== (case inequality) operator [SystemVerilog]. if (words[0]
>> !== words[$]) begin | ncvlog: *E,BDSTRO (sv_queue1.sv
> <http://sv_queue1.sv>
>> <http://sv_queue1.sv>,33|27): Illegal type string right operand
>> to !== (case inequality) operator [SystemVerilog]. module 
>> worklib.main:sv errors: 8, warnings: 0 ncvlog: *F,NOTOPL: no 
>> top-level unit found, must have recursive instances. irun: 
>> *E,VLGERR: An error occurred during parsing.  Review the log
>> file for errors with the code *E and fix those identified
>> problems to proceed.  Exiting with code (status 2).
> 
> 
>> $ irun sv_queue2.sv <http://sv_queue2.sv> <http://sv_queue2.sv>
> irun: 14.10-p001: (c)
>> Copyright 1995-2014 Cadence Design Systems, Inc. file:
> sv_queue2.sv <http://sv_queue2.sv>
>> <http://sv_queue2.sv> 0: if (words[widx] !== "Hello") begin | 
>> ncvlog: *E,BDSTLO (sv_queue2.sv <http://sv_queue2.sv>
> <http://sv_queue2.sv>,18|15):
>> Illegal type string left operand to !== (case inequality)
>> operator [SystemVerilog]. 0: if (words[widx] !== "Hello") begin |
>> ncvlog: *E,TYCMPAT (sv_queue2.sv <http://sv_queue2.sv>
> <http://sv_queue2.sv>,18|33): !== (case
>> inequality) operator types are not equivalent (expecting
>> datatype compatible with 'string' but found 'packed array [39:0]
>> of logic' instead). 1: if (words[widx] !== "World") begin |
>> ncvlog: *E,BDSTLO (sv_queue2.sv <http://sv_queue2.sv>
>> <http://sv_queue2.sv>,23|15):
> Illegal type string
>> left operand to !== (case inequality) operator [SystemVerilog].
>> 1: if (words[widx] !== "World") begin | ncvlog: *E,TYCMPAT 
>> (sv_queue2.sv <http://sv_queue2.sv>
>> <http://sv_queue2.sv>,23|33):
> !== (case inequality)
>> operator types are not equivalent (expecting datatype compatible 
>> with 'string' but found 'packed array [39:0] of logic' instead). 
>> module worklib.main:sv errors: 4, warnings: 0 ncvlog: *F,NOTOPL:
>> no top-level unit found, must have recursive instances. irun: 
>> *E,VLGERR: An error occurred during parsing.  Review the log
>> file for errors with the code *E and fix those identified
>> problems to proceed.  Exiting with code (status 2).
> 
> 
> 
>> On Tue, Jul 22, 2014 at 5:26 AM, Stephen Williams 
>> <st...@ic... <mailto:st...@ic...>
> <mailto:st...@ic... <mailto:st...@ic...>>> wrote:
> 
> 
>> I'm planning on adding SystemVerilog queue objects support to 
>> Icarus Verilog, and to that end I've put together some simple 
>> tests. Can anyone with a Bis-3 SystemVerilog simulator run the 
>> attached example for me?
> 
>> Thanks,
> 
> 
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> 
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> 
> 
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- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
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