Re: [Iverilog-devel] Infinite loop on simulation

[Cary R. <cy...@ya...>]

One significant point of clarification. Your register block is not a S/R flip-flop or even a S/R latch. It is a S/R latch with some extra control logic to make it act like a D latch. This latch is transparent when the enable (set pin) is high. It is not edge sensitive like a D flip-flop. I believe the problem you are experiencing is because you are using a latch like a flip-flop, which as you have discovered doesn't work very well.

Cary

On Tuesday, April 8, 2014 12:54 PM, Stephen Williams <st...@ic...> wrote:
 
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The typical pattern in Verilog for a D-type FF is:

   reg Q;
   always @(posedge clk) Q <= D;

That is the basic atom of pretty much any state machine that you
model in Verilog, so once you get that in your head, things will
go a lot easier for you. Maybe kinda something like this?:

module counter(
   output reg [7:0] count,
   input clk,
   input reset,
   input load,
   input [7:0] load_value);

   always @(posedge clk) begin
      if (reset)
        count <= 0;
      else if (load)
        count <= load_value;
      else if (enable)
        count <= count + 1;
   end

endmodule

On 04/08/2014 12:32 PM, Patrick Samy wrote:
> 2014-04-08 17:15 GMT+01:00 Stephen Williams <st...@ic...>:
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>> 
>> 
>> Just quickly looking at this...
> 
> Thank you for taking the time to do this !
> 
>> It appears that you've created an infinitely fast oscillator.
> 
> Indeed, this simplified code performs an add "xout <- out + 1" and 
> does not store the carry, which therefore oscillates.
> 
> The original code does the same thing but with a 32-bit register
> based on the same D flip-flop and adding 4 to the (t - 1) value.
> 
>> I think you are trying to create an SR flip-flop with the last 
>> two nand gates in your register module, but instead you are
>> getting meta-stability.
> 
> Understood. I thought it could be the issue and you're right, I am 
> trying to create an SR flip-flop storing one bit with my register 
> module.
> 
>> Synchronous logic is not typically modeled in Verilog this way. 
>> This looks like an educational exercise, so you might try
>> getting more realistic relative timings.
>> 
>> What are you really trying to do?
> 
> I am designing a program counter component for my
> microarchitecture.
> 
> Ok, so do you mean that I should be using _always @(posedge
> clock)_ type of statements instead ?
> 
> In my original code, I was generating the clock with the following 
> code but I had the same issue:
> 
> always begin #5 clock = ~clock; end
> 
> Thanks again.
> 
> Regards,
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
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