Re: [Iverilog-devel] Infinite loop on simulation

[Cary R. <cy...@ya...>]

This is a problem in your design/test setup. I could tell you the problem and I will if you really want, but a better way is to learn some debugging techniques.

Adding the following line to the register module will show you the state of the bits driving the latch element:

always @(qi, not_qi) $display($time,, in,, set,, qi,, not_qi);

If you don't know, in the Icarus run time (vvp) ^C followed by finish<CR> will stop the simulation. What pattern do you see?The key question here is why is "in" toggling? The answer to that is found by evaluating the connection of the gates at the test level when the top level "in" == 0 (which is not the same as the register "in" signal).


If your gates had some delay the simulation would not lock up at a specific time step, but it will not stop either. You would need to end the test block with clock == 0 or add an explicit $finish.

I hope that helps.

Cary

On Tuesday, April 8, 2014 9:16 AM, Stephen Williams <st...@ic...> wrote:
 
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Just quickly looking at this...

It appears that you've created an infinitely fast oscillator.
I think you are trying to create an SR flip-flop with the last
two nand gates in your register module, but instead you are getting
meta-stability.

Synchronous logic is not typically modeled in Verilog this way.
This looks like an educational exercise, so you might try getting
more realistic relative timings.

What are you really trying to do?

On 04/08/2014 03:50 AM, Patrick Samy wrote:
> Hello,
> 
> When I perform a simulation of my design with iverilog 0.9.7, it
> seems to be stuck in an infinite loop.
> 
> The original design is a program counter adder with the following
> prototype:
> 
> module program_counter(input enable_count, input enable_overwrite, 
> input[31:0] overwrite_value, output[31:0] out);
> 
> I managed to simplify the verilog testbench code with a D flip flop
> as a 1-bit register and reproduce the issue:
> 
> module register(input in, input set, output out);
> 
> wire not_in; wire qi; wire not_qi; wire not_q;
> 
> nand (qi, in, set);
> 
> not  (not_in, in); nand (not_qi, not_in, set);
> 
> nand (out, qi, not_q); nand (not_q, not_qi, out);
> 
> endmodule
> 
> module test;
> 
> reg  clock; reg  in; wire out; wire not_out;
> 
> // add 'x_out <- out + 1' xor (x_out, out, 1);
> 
> // 2x1 mux with 'in' as value and control bit or  (muxed_out,
> x_out, in);
> 
> register r(muxed_out, clock, out);
> 
> initial begin $dumpfile("test.vcd"); $dumpvars(0, test);
> 
> $display("\tclock,\tin,\tout") ; $monitor("\t%b,\t%x,\t%b", clock,
> in, out);
> 
> // erase internal register #0 in = 1; #0 clock = 1;
> 
> #1 in = 0; #1 clock = 0;
> 
> #2 clock = 1; #3 clock = 0; #4 clock = 1; end
> 
> endmodule
> 
> 
> The VCD output does not show any change of state after the #2
> tick: in== 0 clock == 1
> 
> Therefore, the register is continuously feeded with the result of
> the adder and my guess is that icarus is waiting for the values to 
> stabilize for this tick and gets stuck.
> 
> Can you spot a potential issue with this design ?
> 
> I also posted the issue on StackOverflow to make sure that code is
> correct: 
> http://stackoverflow.com/questions/22900633/infinite-loop-when-simulating-a-program-counter-design-with-icarus-verilog
>
>  Thanks and apologies in advance if this is a stupid mistake on my 
> side, I spent a week trying to figure it out by myself without 
> success.
> 
> Regards,
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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