Re: [Iverilog-devel] instantiating undefined modules

[Martin W. <mai...@ma...>]

Martin Whitaker wrote:
> To expand a bit on what Steve said, for each library component you need to
> create a module that just defines the input/output pins of that component. For
> example:
>
>     module 74LS245(
>       input       nEN,
>       input       DIR,
>       inout [8:1] A,
>       inout [8:1] B
>     );
>     endmodule
>
And of course, to be legal Verilog, the module name must start with a letter 
or an underscore, so you would need to change this example to get it to compile.