[Iverilog-devel] instantiating undefined modules

[Cotton S. <co...@al...>]

Is there a mechanism in iverlog to elaborate a design that instantiates
an undefined/external module?  Obviously, I don't intend to simulate it.
 I'm potentially interested in using verilog rather than schematic
capture to do PCB design.  There would need to be a library of discrete
components, but I'm not sure how to declare such a thing in verilog.
(I'm still relatively new to verilog.  My apologies if my question is
naive.)  A backend would convert the iverlog netlist to a netlist for
something like Kicad.

Best,
Cotton