Re: [Iverilog-devel] SystemVerilog, continuous assignment and unpacked arrays

[Michael S. <mic...@gm...>]

After changing Q from wire to reg both ncsim and vcs passed.

Best regards,
Michael Strelnikov


On 13 March 2014 13:58, Stephen Williams <st...@ic...> wrote:

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> I cannot find any clarity on this in the IEEE1800 LRM. It seems
> to imply that continuous assignments of unpacked arrays are OK,
> as long as there is only a single driver. The attached test
> program tries to test that. Of course, the current Icarus Verilog
> reports an error on this, but I think big name SystemVerilog
> compilers will handle it.
>
> Can someone test this for me?
>
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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