[Iverilog-devel] vec4-stack progress

[Stephen W. <st...@ic...>]

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I've updated the vecr-stack branch. I've merged the current master
changes that have been happening, and I've fixed up some expression
width issues. This is getting pretty close to the master, now. There
are only about a dozen tests left that pass the master and not the
vec4 branch.

One visible change has been that the vec4 branch hews more closely
to the standard for unsized numbers that are narrower then 32bits.
This has been a nagging issue for many people, so I'm taking this
opportunity to relent. Unsized literals will be widened to at least
32bits, although I'll still allow for more if needed to preserve
the value.

There have been reports that the vec4-stack branch runs slower,
but I think there is lots of room for optimization, so I'm not
worried about that yet. Overall, I think the result is cleaner
and will be faster after some obvious inefficiencies are cleaned
up.

I want to merge this into master soon, because it is getting
increasingly difficult to maintain separate master and vec4
branches.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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