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From: Iztok J. <izt...@gm...> - 2014-02-19 10:40:48
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$ irun sv_unpacked_port.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_unpacked_port.sv
module worklib.test:sv
errors: 0, warnings: 0
module worklib.main:sv
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Top level design units:
main
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.main:sv <0x1e933575>
streams: 3, words: 2825
worklib.test:sv <0x6e825af1>
streams: 2, words: 349
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 2 2
Registers: 5 5
Scalar wires: 1 -
Vectored wires: 3 -
Always blocks: 1 1
Initial blocks: 1 1
Pseudo assignments: 2 2
Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
On Tue, Feb 18, 2014 at 6:05 PM, Stephen Williams <st...@ic...> wrote:
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> On 02/18/2014 02:13 AM, Iztok Jeras wrote:
> > The 'sv_unpacked_port.sv <http://sv_unpacked_port.sv>' needed some
> > more changes. Array sizes where only the size [width-1], not the
> > range [width-1:0] are specified, are only allowed for the unpacked
> > part of the array, so on the right side. Also the address was
> > missing from the list in the display line. I did not check the
> > intention of the test.
>
> OK, The sv_unpacked_port.sv test needed more work, so I've attached
> an update. This should fix it, and it should display "PASSED".
>
> Thanks for running these tests.
> - --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
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