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Re: [Iverilog-devel] Some Sample SystemVerilog programs
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From: Iztok J. <izt...@gm...> - 2014-02-18 10:13:52
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The 'sv_typedef_scope.sv' issue was a trivial typo. The 'sv_unpacked_port.sv'
needed some more changes. Array sizes where only the size [width-1], not
the range [width-1:0] are specified, are only allowed for the unpacked part
of the array, so on the right side. Also the address was missing from the
list in the display line. I did not check the intention of the test.
Updated test files are attached, so you can check the diff.
Regards,
Iztok Jeras
$ irun sv_typedef_scope.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_typedef_scope.sv
module worklib.main:sv
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Top level design units:
$unit_0x3fdf4418
main
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.main:sv <0x5a44e65c>
streams: 1, words: 1444
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 1 1
Initial blocks: 1 1
Compilation units: 1 1
Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
$ irun sv_unpacked_port.sv
irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: sv_unpacked_port.sv
module worklib.test:sv
errors: 0, warnings: 0
module worklib.main:sv
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Top level design units:
main
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.main:sv <0x1e933575>
streams: 3, words: 2672
worklib.test:sv <0x6e825af1>
streams: 2, words: 349
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 2 2
Registers: 5 5
Scalar wires: 1 -
Vectored wires: 3 -
Always blocks: 1 1
Initial blocks: 1 1
Pseudo assignments: 2 2
Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
ncsim> run
FAILED -- data[1]==01, Q==00
Simulation complete via $finish(1) at time 4 NS + 0
./sv_unpacked_port.sv:41 $finish;
ncsim> exit
On Tue, Feb 18, 2014 at 11:02 AM, Iztok Jeras <izt...@gm...> wrote:
> $ irun sv_for_variable.sv
> irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
> file: sv_for_variable.sv
> program worklib.main:sv
> errors: 0, warnings: 0
> Caching library 'worklib' ....... Done
> Elaborating the design hierarchy:
> Top level design units:
> main
> Building instance overlay tables: .................... Done
> Generating native compiled code:
> worklib.main:sv <0x0d85b4f9>
> streams: 1, words: 900
> Building instance specific data structures.
> Loading native compiled code: .................... Done
> Design hierarchy summary:
> Instances Unique
> Programs: 1 1
> Registers: 3 3
> Initial blocks: 1 1
> Writing initial simulation snapshot: worklib.main:sv
> Loading snapshot worklib.main:sv .................... Done
> ncsim> source /tools/opt/cadence/INCISIV13.10.014/tools/inca/files/ncsimrc
> ncsim> run
> PASSED
> Simulation complete via implicit call to $finish(1) at time 0 FS + 1
> ./sv_for_variable.sv:2 program main;
> ncsim> exit
>
>
> $ irun sv_typedef_scope.sv
> irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
> file: sv_typedef_scope.sv
> module worklib.main:sv
> errors: 0, warnings: 0
> Caching library 'worklib' ....... Done
> Elaborating the design hierarchy:
> Top level design units:
> $unit_0x3fdf4418
> main
> if (foo.log_x !== 3'b000) begin
> |
> ncelab: *E,CUVUNF (./sv_typedef_scope.sv,35|18): Hierarchical name
> component lookup failed at 'log_x'.
> irun: *E,ELBERR: Error during elaboration (status 1), exiting.
>
>
> $ irun sv_unpacked_port.sv
> irun: 13.10-s014: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
> file: sv_unpacked_port.sv
> module worklib.test:sv
> errors: 0, warnings: 0
> logic [width-1] data [0:3];
> |
> ncvlog: *E,SVPKSN (sv_unpacked_port.sv,21|17): The single-bound form of a
> range is only allowed for array (i.e., unpacked) dimensions.
> wire [width-1] Q;
> |
> ncvlog: *E,SVPKSN (sv_unpacked_port.sv,23|16): The single-bound form of a
> range is only allowed for array (i.e., unpacked) dimensions.
> module worklib.main:sv
> errors: 2, warnings: 0
> irun: *E,VLGERR: An error occurred during parsing. Review the log file
> for errors with the code *E and fix those identified problems to proceed.
> Exiting with code (status 1).
>
>
> I will try to fix the code if the errors are obvious.
>
> Regards,
> Iztok Jeras
>
>
> On Tue, Feb 18, 2014 at 5:17 AM, Stephen Williams <st...@ic...>wrote:
>
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA1
>>
>>
>> Hi all,
>>
>> I'm looking at some more SystemVerilog features, and I would like
>> to check some test programs with some Big-3 simulators to make
>> sure I really am understanding things correctly. I've attached
>> the example that I'm planning to make work. Can someone send me
>> results from some other tools?
>>
>> Thanks,
>>
>> - --
>> Steve Williams "The woods are lovely, dark and deep.
>> steve at icarus.com But I have promises to keep,
>> http://www.icarus.com and lines to code before I sleep,
>> http://www.picturel.com And lines to code before I sleep."
>> -----BEGIN PGP SIGNATURE-----
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>> fQMAn0DnI3sx2wvHyvW6u98e0vabcMNb
>> =Wa0G
>> -----END PGP SIGNATURE-----
>>
>>
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>
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