Re: [Iverilog-devel] vec4-stack progress

[Stephen W. <st...@ic...>]

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Woah, that's interesting. (The performance hit, I mean.)

It is true, though, that some of the translation is simplistic,
and my expectation is that with some optimization I should be
able to turn that around. For example, I have done NO profiling
yet. There are a few tests in the ivtest suite that broke, and
I want to address those first, but then I want to do some profiles
to really see what's bad. Honestly, I think I can get it faster
than the existing mode.

On 02/14/2014 12:41 PM, Martin Whitaker wrote:
> Running the subset of my production tests that Icarus can handle
> has not exposed any functional bugs. However, selecting a
> moderately sized test, I'm seeing ~32% increase in run time and
> ~10% increase in number of vvp instructions. This is too big a
> performance hit for my liking.
> 
> Martin
> 
> Stephen Williams wrote:
> 
> The vec4-stack branch of Icarus Verilog in the git repository is
> almost complete. I've been merging in updates to master, so it has
> been keeping up with other changes.
> 
> The actual vec4 work is almost complete; there are only a few 
> unusual corner cases that are not working, so I think it is ready
> for folks to start trying it out. I'm not going to merge it into
> master until it passes ALL the ivtest tests that master current
> passes (there are a handful that fail) but it is really close and I
> would like to get it out there for people to mess with.
> 
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- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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