Re: [Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> Yep, that's an Icarus Verilog bug and needs to be filed.
> ISim is correct that 2'b10 + 2'b10 == 2'b00.
>
> On 01/21/2014 10:19 AM, Sébastien Bourdeauducq wrote:
>> On 01/21/2014 07:17 PM, Stephen Williams wrote:
>>>> $display("%b", 2'd2 + 2'd2);
>>> I'm actually surprised that this displays 100, as that is 3 bits,
>>>   and the expression is only 2 bits.
>>
>> FWIW Xilinx ISim displays 00 here.

I'm guessing this is using v0.9. Development gives the correct result. There 
are a lot of expression width bugs in v0.9 which are fixed in development.

Martin