Re: [Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Stephen W. <st...@ic...>]

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Yep, that's an Icarus Verilog bug and needs to be filed.
ISim is correct that 2'b10 + 2'b10 == 2'b00.

On 01/21/2014 10:19 AM, Sébastien Bourdeauducq wrote:
> On 01/21/2014 07:17 PM, Stephen Williams wrote:
>>> $display("%b", 2'd2 + 2'd2);
>> I'm actually surprised that this displays 100, as that is 3 bits,
>>  and the expression is only 2 bits.
> 
> FWIW Xilinx ISim displays 00 here.
> 
> 
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- -- 
Steve Williams                "The woods are lovely, dark and deep.
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