Re: [Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Sébastien B. <seb...@le...>]

On 01/21/2014 07:17 PM, Stephen Williams wrote:
>> $display("%b", 2'd2 + 2'd2);
> I'm actually surprised that this displays 100, as that is 3 bits, 
> and the expression is only 2 bits.

FWIW Xilinx ISim displays 00 here.