Re: [Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Stephen W. <st...@ic...>]

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On 01/21/2014 09:24 AM, Sébastien Bourdeauducq wrote:
> Hi,
> 
> Running the following:
> 
> $display("%b", 2'd2 + 2'd2);

I'm actually surprised that this displays 100, as that is 3 bits,
and the expression is only 2 bits.

> $display("%b", 3'd4 >= 2'd1);

Yeah, that's fine. 3'b100 >= 2'b01  ---> 1'b1

> $display("%b", (2'd2 + 2'd2) >= 2'd1);

This is right: (2'b10 + 2'b10) >= 2'b01
Both sides are 2bits wide, and 10+10 == (1)00 == 2'b00, which
is not >= 01. The size of arithmetic expressions is the size
of the largest operand, in the case of "+" in your example,
that is 2bits.


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