[Iverilog-devel] Weird behaviour of Verilog addition/comparison

[Sébastien B. <seb...@le...>]

Hi,

Running the following:

$display("%b", 2'd2 + 2'd2);
$display("%b", 3'd4 >= 2'd1);
$display("%b", (2'd2 + 2'd2) >= 2'd1);

produces this output:

100 (ok)
1 (ok)
0 (wtf?!)

The Verilog standard says that when comparing operands of different
lengths, the smaller one should be extended (I guess, sign-extended).

Is there yet another Verilog idiosyncrasy that I have missed out (e.g.
the right hand side of the comparison defines the width for the
addition), or is this a bug in Icarus Verilog?

Sébastien