Re: [Iverilog-devel] Yet another SystemVerilog test

[Jared C. <jar...@gm...>]

All three tests pass in ModelSim 10.0a and VCS G-2012.09-3 as well.

Jared

On Wed, Dec 11, 2013 at 6:39 PM, Stephen Williams <st...@ic...> wrote:
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> This is actually a set of tests that check my understanding of
> how the $root scope should work for certain types of typedefs.
> I've encountered syntax like this in customer code so I'm pretty
> sure it is correct, but I'd like to have these programs in
> particular checked, just to be sure.
>
> Thanks,
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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