Re: [Iverilog-devel] Yet another SystemVerilog test

[Iztok J. <izt...@gm...>]

$ irun sv_union1b.sv
irun: 13.10-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
file: sv_union1b.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        $unit_0x06988e28
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x3f23628f>
            streams:   1, words:  1093
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Initial blocks:     1       1
        Compilation units:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.008/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit


$ irun sv_union2b.sv
irun: 13.10-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
file: sv_union2b.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        $unit_0x069c2138
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x4f0d5546>
            streams:   1, words:  1097
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Initial blocks:     1       1
        Compilation units:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.008/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit


$ irun sv_union3b.sv
irun: 13.10-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
file: sv_union3b.sv
    module worklib.main:sv
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        $unit_0x069fb448
        main
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.main:sv <0x3d228bc6>
            streams:   1, words:  1089
    Building instance specific data structures.
    Loading native compiled code:     .................... Done
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Initial blocks:     1       1
        Compilation units:  1       1
    Writing initial simulation snapshot: worklib.main:sv
Loading snapshot worklib.main:sv .................... Done
ncsim> source /tools/opt/cadence/INCISIV13.10.008/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit




On Thu, Dec 12, 2013 at 3:39 AM, Stephen Williams <st...@ic...> wrote:

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> This is actually a set of tests that check my understanding of
> how the $root scope should work for certain types of typedefs.
> I've encountered syntax like this in customer code so I'm pretty
> sure it is correct, but I'd like to have these programs in
> particular checked, just to be sure.
>
> Thanks,
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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>
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