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Re: [Iverilog-devel] $random(seed)/some code to test
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From: Cary R. <cy...@ya...> - 2013-09-06 23:40:15
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Hi Jared,
Just so you know the libc random functions have nothing to do with/are not used by the Verilog random functions.
We could add a $srandom or $ivl_srandom to set the seed for plain $random calls. This would allow us to change the code to match the other simulators and a simple `ifdef __ICARUS__ could be used to get the functionality you would like for $random. The problem with $srandom or $random setting the hidden seed is the user must guarantee it is called before calling a plain $random. That's probably why the standard specifically says the seed must be set before the first call to $random(seed). Which makes it the users responsibility to get the initialization/calling order correct.
I believe much of this is fixed in SystemVerilog if you use constrained random variable where a srandom method is available.
Cary
________________________________
From: Jared Casper <jar...@gm...>
To: Cary R. <cy...@ya...>
Cc: Discussions concerning Icarus Verilog development <ive...@li...>
Sent: Friday, September 6, 2013 1:03 PM
Subject: Re: [Iverilog-devel] $random(seed)/some code to test
In libc, there are two different sets of functions to call depending
on where you want the random state to be. If you want the system to
keep the state (and thus only have one sequence of random numbers),
you use rand(), optionally setting the state with srand() (or the
equivalent random/srandom, seed48/drand48/etc.). If you want to keep
your own state in user code (allowing for multiple independent
sequences), you use rand_r() (or erand48/etc.).
With Verilog's $random function (as I understand it) the random state
can be in either the user code or the system. The state is in the
system when you just use $random() with no seed. The state is in user
code by using the same seed variable for each call to $random(seed)
(note that you can have multiple state variables for multiple
sequences). In Icarus and VCS you can change the system state used
by bare random calls using $random(seed), giving you an equivalent to
libc's srandom() and allowing you to set the seed used by bare $random
calls. So you can still have the system keep the state for you with
the ability to set the initial seed value. In nc/modelsim/gplcver, it
appears you don't have this option, either you keep the state
yourself, or you use the default seed value of bare $random calls.
There is no equivalent to srandom() in that implementation.
I personally prefer Icarus's implementation, as it allows you to set
the seed in one place, and just use bare $random in various modules
getting consistent but changeable random sequences. With nc/ModelSim,
it would be more difficult to give the simulation a single random seed
and have everything repeat as before using that seed when there are
$random calls in different modules. I also have the option to have
multiple independent sequences in Icarus by using different seed
variables that are always supplied, just as I do with nc/ModelSim.
Jared
On Fri, Sep 6, 2013 at 12:18 PM, Cary R. <cy...@ya...> wrote:
> Thanks Jared,
>
> From these results and with some thought and testing here's the difference
> and this is probably a subtle bug in Icarus and VCS.
>
> When a seed variable is used ncverilog/Modelsim/gplcver do not set the
> internal seed value that a plain call to $random uses. It only uses the seed
> variable. Icarus and VCS set this hidden seed value to the provided seed
> value. So for ncverilog/ModelSim/gplcver calls to plain $random always start
> with a seed of zero and are not effected to by calls to $random with a seed.
> This is a trivial fix if we all agree that this should be changed. I think
> it probably should be changed. The next question is if we do this change
> should it be back ported to V0.9? For portability sake it should, but it
> will produce different results.
>
> Cary
>
> ________________________________
> From: Jared Casper <jar...@gm...>
> To: Cary R. <cy...@ya...>; Discussions concerning Icarus Verilog
> development <ive...@li...>
> Sent: Friday, September 6, 2013 11:14 AM
> Subject: Re: [Iverilog-devel] $random(seed)/some code to test
>
> VCS Compiler version G-2012.09-3_Full64; Runtime version
> G-2012.09-3_Full64; Sep 6 10:38 2013
> 1 2 => -2147345408
> 2 138139 -> -1196295055
> 3 138139 -> -363270956
> 4 138139 -> 416079665
> 1a 138139 => -1196295055
> 2a 951188000 -> -363270956
> 3a 951188000 -> 416079665
> 4a 951188000 -> 540214080
>
>
> ncverilog: 08.20-s006: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
> 1 2 => -2147345408
> 2 138139 -> 303379748
> 3 138139 -> -1064739199
> 4 138139 -> -2071669239
> 1a 138139 => -1196295055
> 2a 951188000 -> -1309649309
> 3a 951188000 -> 112818957
> 4a 951188000 -> 1189058957
>
> # // ModelSim SE 10.0a Feb 21 2011 Linux 2.6.32-279.14.1.el6.x86_64
> # 1 2 => -2147345408
> # 2 138139 -> 303379748
> # 3 138139 -> -1064739199
> # 4 138139 -> -2071669239
> # 1a 138139 => -1196295055
> # 2a 951188000 -> -1309649309
> # 3a 951188000 -> 112818957
> # 4a 951188000 -> 1189058957
> (ISim from Xilinx ISE 14.6 gives the same as above)
>
> For completeness, I get this from Icarus, which matches VCS
> 1 2 => -2147345408
> 2 138139 -> -1196295055
> 3 138139 -> -363270956
> 4 138139 -> 416079665
> 1a 138139 => -1196295055
> 2a 951188000 -> -363270956
> 3a 951188000 -> 416079665
> 4a 951188000 -> 540214080
>
> It seems VCS does what Icarus does while NC and ModelSim don't repeat.
>
> Jared
>
> On Fri, Sep 6, 2013 at 10:23 AM, Cary R. <cy...@ya...> wrote:
>> Hi Stephan,
>>
>> My first inclination would be yes. I created a simple example and tested
>> it
>> with gplcver, veriwell and Icarus and for the most part all three gave
>> different results for the $random function, but the seed values were the
>> same. I was certainly not expecting this. I am attaching the code so we
>> can
>> see what other name brand simulators report. $random and seeding is
>> further
>> complicated in continuous assignment code, but I think that is part of the
>> reason constrained random variables were introduced in SystemVerilog. Once
>> we have the results from other simulators we can discuss this more.
>>
>> Cary
>>
>> ________________________________
>> From: Stephan Boettcher <boe...@ph...>
>> To: Discussions concerning Icarus Verilog development
>> <ive...@li...>
>> Sent: Friday, September 6, 2013 2:03 AM
>> Subject: [Iverilog-devel] $random(seed)
>>
>>
>> Hi,
>>
>> I was looking at how $random(seed) is implemented. As I read the code,
>> if there are calls with an explicit seed argument, mixed with calls
>> without an explicit seed, like
>>
>> a = $random(seed),
>> b = $random;
>> c = $random(seed);
>>
>> b and c will be the same. Is that intended behaviour?
>>
>> Stephan
>>
>>
>> static PLI_INT32 sys_random_calltf(ICARUS_VPI_CONST PLI_BYTE8 *name)
>> {
>> vpiHandle callh, argv, seed = 0;
>> s_vpi_value val;
>> static long i_seed = 0;
>>
>> /* Get the argument list and look for a seed. If it is there,
>> get the value and reseed the random number generator. */
>> callh = vpi_handle(vpiSysTfCall, 0);
>> argv = vpi_iterate(vpiArgument, callh);
>> val.format = vpiIntVal;
>> if (argv) {
>> seed = vpi_scan(argv);
>> vpi_free_object(argv);
>> vpi_get_value(seed, &val);
>> i_seed = val.value.integer;
>> }
>>
>> /* Calculate and return the result. */
>> val.value.integer = rtl_dist_uniform(&i_seed, INT_MIN, INT_MAX);
>> vpi_put_value(callh, &val, 0, vpiNoDelay);
>>
>> /* If it exists send the updated seed back to seed parameter. */
>> if (seed) {
>> val.value.integer = i_seed;
>> vpi_put_value(seed, &val, 0, vpiNoDelay);
>> }
>>
>> return 0;
>> }
>>
>> --
>> Stephan Böttcher Tel: +49-431-880-2508
>> Extraterrestrische Physik
>> I.f.Exp.u.Angew.Physik
>> Leibnizstr. 11, 24118 Kiel, Germany
>>
>>
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