Re: [Iverilog-devel] Generate scope change in vvp and the VPI API for development

[Iztok J. <izt...@gm...>]

Hi,

I added a C++ bench wrapper for verilator. The example produces a VCD file,
containing the interface visible only as a module.
./wav_interface.verilator.sh
gtkwave wav_interface.vcd
The same approach could be used by icarus when exporting to VCD. But for
FST I would really like to see the interfaces also visible as a ports with
directions specified by modports.

I must say I am a bit impressed with Verilator support for interfaces.

Regards,
Iztok Jeras


On Sat, Jul 27, 2013 at 6:55 PM, Iztok Jeras <izt...@gm...> wrote:

> Hi Tony,
>
> I now added the interface example. The hierarchy is a bit more complex
> here. The bench part and the RTL parts are separated, and there are no SV
> interfaces between them, only normal signals. This is because I would like
> to compile this example in Verilator (it is already passing "verilator
> --lint-only wav_interface.sv"), and interfaces are kind of not allowed as
> top level module ports (I do not know what the standard has to say, but
> tools are reporting issues). Inside the top level RTL module
> 'wav_interface' there is an instance of the streaming protocol interface
> 'wav_interface_str'. This interface is then connected to a stream source
> module 'wav_interface_src' instance and a stream drain module
> 'wav_interface_drn' instance. The interface contains modports, which are
> used to specify the direction of signals if the interface is used as a
> module port. I wrote a source and a drain modport, but it is common to add
> a passive modport for bus monitors (all signals are inputs into the
> monitor).
>
> Till now I observed interfaces using INCISIVE (the latest) and ModelSim
> Altera, and I am not satisfied with them. What I would expect, is first for
> the interface instance being visible similarly to a module, this is done
> well by both tools. Next I would like to see the interfaces as module
> ports, including the directions specified in modports, this is not done
> that well by the mentioned tools. ModelSim seems to show the interface as a
> module instance inside the module which should have it as s port, and no
> related port signals are listed. INCISIVE simvision sometimes shows the
> interface ports properly, but it depends how you specify the simulation
> environment. I noticed this while playing with large projects containing
> UVM, so I do not have an easy explanation here.
>
> If you are going to work on this, it makes sense to first try and see how
> other tools handle it.
>
> I am curious to see how verilator dumps this example into a VCD file, but
> I am not experienced enough with verilator to do it quickly.
>
> The sources are:
> bench: wav_interface_tb.sv (top module: wav_interface_tb)
> RTL: wav_interface.sv (top module: wav_interface)
>
> Regards,
> Iztok Jeras
>