Re: [Iverilog-devel] Generate scope change in vvp and the VPI API for development

[Jared C. <jar...@gm...>]

On Wed, Jul 24, 2013 at 1:21 PM, Martin Whitaker
<mai...@ma...> wrote:
> I'm definitely interested in this - I make extensive use of net arrays.
>

I'll hopefully get to it within a week or so and see how far I get...

> It might be worth mentioning that the default behaviour of NC-Verilog is to
> dump the elements of a net array when $dumpvars is called. For example, with
> the declaration
>
>    wire [7:0] Out[0:1][0:1];
>

I definitely remember some discussion on this a while back.  IIRC the
decision was that including memories in $dumpvars by default it would
be too easy to dump huge amount of values and slow things down to a
halt (among other reasons?).  Seems reasonable to me to include net
arrays by default but not var arrays (i.e. memories).   The standard
isn't explicit as far as I can see, it just says $dumpvars should dump
"all the variables".  For now I'll put things into a $dumpmems but
shouldn't be hard to change it later...

> the VCD file contains
>
>    $var wire      8 !    Out [0][0] $end
>    $var wire      8 "    Out [0][1] $end
>    $var wire      8 #    Out [1][0] $end
>    $var wire      8 $    Out [1][1] $end
>
> Unfortunately this syntax confuses gtkwave!
>

You might be able to get by with a sed script to escape the
identifiers (i.e. "\Out[0][1]"), which gtkwave accepts.

Jared