Re: [Iverilog-devel] Generate scope change in vvp and the VPI API for development

[Martin W. <mai...@ma...>]

Jared Casper wrote:
> I'm dealing now with a design that makes extensive use of net arrays.
> Rather then going through and manually looping through each array and
> dumping each element as an individual net, I've been planning to go in
> and implement a $dumpmems parallel and similar to $dumpvars that
> creates a new scope for each array and puts each element in there. My
> plan is to just hack something up for myself so my dump files are a
> little cleaner (and I don't need to manually put in dozens of for
> loops), then if there is interest I could clean it up and put in a
> patch.  I know previous discussion has decided that $dumpvars should
> not dump arrays, but I figured it might be nice to have a $dumpmems or
> something to do so, probably with a little more control so things
> don't get out of hand.  This is similar to one way that vcs does it,
> they have a $vcdplusmemon function that turns on dumping of memories,
> it takes a scope, or a specific array and list of dimension bounds to
> dump.  The fsdb dumper takes in an extra argument that indicates that
> arrays should be included (i.e. "+mda"), but since Icarus uses the
> standard $dumpvars function names, this doesn't seem like an option.
>
I'm definitely interested in this - I make extensive use of net arrays.

It might be worth mentioning that the default behaviour of NC-Verilog is to 
dump the elements of a net array when $dumpvars is called. For example, with 
the declaration

   wire [7:0] Out[0:1][0:1];

the VCD file contains

   $var wire      8 !    Out [0][0] $end
   $var wire      8 "    Out [0][1] $end
   $var wire      8 #    Out [1][0] $end
   $var wire      8 $    Out [1][1] $end

Unfortunately this syntax confuses gtkwave!

Martin