Re: [Iverilog-devel] iverilog bug: module output treated as input

[Martin W. <mai...@ma...>]

Yes, the simulator's behaviour is correct. The relevant sentence is in section 
12.3.8 of the 1364-2005 standard:

"A port that is declared as input (output) but used as an output (input) or 
inout may be coerced to inout. If not coerced to inout, a warning has to be 
issued."

I first encountered this "feature" in Verilog-XL, many years ago.

Martin

Stephan Boettcher wrote:
>
> Hi,
>
> I had a discrepancy between simulation and target behavior that was
> caused by an input which was erroneously declared as output.  In
> simulation with iverilog it worked without any warnings.
>
> Altera Quartus removed a lot of logic because it found no drivers for
> the intended input signal, also without much warning.
>
> Is the simulator's behaviour correct?  Sorry if this is a known issue.
>
> Stephan
>
>
>
>
> (stephan)falbala:~/icarus$ /usr/local/bin/iverilog -v -Wall ioport.v -o ioport.vvp
> Icarus Verilog version 0.10.0 (devel) (s20121218-148-g1b1aa06)
>
> Copyright 1998-2013 Stephen Williams
>
>    This program is free software; you can redistribute it and/or modify
>    it under the terms of the GNU General Public License as published by
>    the Free Software Foundation; either version 2 of the License, or
>    (at your option) any later version.
>
>    This program is distributed in the hope that it will be useful,
>    but WITHOUT ANY WARRANTY; without even the implied warranty of
>    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>    GNU General Public License for more details.
>
>    You should have received a copy of the GNU General Public License along
>    with this program; if not, write to the Free Software Foundation, Inc.,
>    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
>
> translate: /usr/local/lib/ivl/ivlpp  -v -L -F"/tmp/ivrlg22758551f" -f"/tmp/ivrlg2758551f" -p"/tmp/ivrli2758551f"  | /usr/local/lib/ivl/ivl -v -C"/tmp/ivrlh2758551f" -C"/usr/local/lib/ivl/vvp.conf" -- -
> Icarus Verilog Preprocessor version 0.10.0 (devel) (s20121218-148-g1b1aa06)
>
> Copyright (c) 1999-2011 Stephen Williams (st...@ic...)
>
>    This program is free software; you can redistribute it and/or modify
>    it under the terms of the GNU General Public License as published by
>    the Free Software Foundation; either version 2 of the License, or
>    (at your option) any later version.
>
>    This program is distributed in the hope that it will be useful,
>    but WITHOUT ANY WARRANTY; without even the implied warranty of
>    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>    GNU General Public License for more details.
>
>    You should have received a copy of the GNU General Public License along
>    with this program; if not, write to the Free Software Foundation, Inc.,
>    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
> /usr/local/lib/ivl/system.sft: Processing System Function Table file.
> /usr/local/lib/ivl/vhdl_sys.sft: Processing System Function Table file.
> /usr/local/lib/ivl/v2005_math.sft: Processing System Function Table file.
> /usr/local/lib/ivl/va_math.sft: Processing System Function Table file.
> Using language generation: IEEE1364-2005,no-specify,xtypes,icarus-misc
> PARSING INPUT
> LOCATING TOP-LEVEL MODULES
>     test
>   ... done, 0 seconds.
> ELABORATING DESIGN
>   ... done, 0 seconds.
> RUNNING FUNCTORS
>   -F cprop ...
>   ... Iteration detected 0 optimizations.
>   ... Look for dangling constants
>   ... done
>   -F nodangle ...
>   ... scan for dangling signal and event nodes. (scomplete=F, ecomplete=F)
>   ... 1 iterations deleted 0 dangling signals and 0 events.
>   ... scan for dangling signal and event nodes. (scomplete=T, ecomplete=F)
>   ... 2 iterations deleted 0 dangling signals and 0 events.
>   ... done
> CALCULATING ISLANDS
>   ... done, 0 seconds.
> CODE GENERATION
>   ... invoking target_design
>   ... done, 0 seconds.
> STATISTICS
> lex_string: add_count=54 hit_count=42
>
> (stephan)falbala:~/icarus$ ./ioport.vvp
> output i=1
> output i=0
> FAILED
>
>
>
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