Re: [Iverilog-devel] verilogams support

[al d. <ad...@fr...>]

On Saturday 25 May 2013, Dezai G wrote:
> Gnucap might handle the Verilog-A code-

The current status of Gnucap and Verilog-AMS .....

Gnucap directly supports the structural subset of Verilog-(*).

Gnucap also supports plugins, so new devices can be added by the 
user at run time.  Gnucap also supports, in a limited 
inefficient way, event driven gate level digital simulation.

Gnucap also supports automatic insertion of connectmodules.  It 
always has, making Gnucap the first simulator ever to implement 
automatic insertion of connectmodules, long before Verilog-A 
existed.  Gnucap's implementation is much more elegant than what 
is described in the Verilog-AMS manual.

A connectmodule is to a regular module (in Verilog-AMS) as a 
union is to a struct (in C).  That is, the only difference is 
that the ports overlay each other in a connectmodule rather than 
being unique.

Unfortunately, there are no Free compilers that support mixed 
analog and digital Verilog, so the connectmodules must be coded 
manually.

The behavioral part requires an external compiler to support.  
This is necesarily that way, because only a true compiler can 
deliver the requried run speed.

Felix Salfelder has a version of ADMS in progress that generates 
C++ code for a native gnucap model.  I think it is nearly ready 
for release, but I have not tested it myself.

Laurent Lemitare also claims to have a version of ADMS that 
generates gnucap code.  I am not sure how complete this is.

Either way, ADMS generates C++, use g++ to compile it to a .so.  
This can be easily automated with a Makefile, so ultimately (not 
far off) you will be able to "load my-model.vams" to add the 
behavioral model.

ADMS has a few significant shortfalls here.  It only implements 
a subset of Verilog-A, aimed at implementing compact analog 
device models.  There is no digital capability, which means it 
cannot be used to compile connectmodules.  A more subtle 
shortfall is that it does not implement cross-events, which are 
important for gnucap's time step control.

There is a work-in-progress, now stalled, unreleased, to make a 
Verilog syntax version of gnucap-modelgen.  I am not sure where 
this will go.  It is stalled because of some personal issues at 
home, and because ADMS seemed to be a more expedient path for 
now.

Gnucap can also use unmodified Spice C device models as plugins, 
through a wrapper (spice-wrapper.cc).  This means all of the 
BSIM models from Berkeley can be used.  Also, most NGspice 
models can be used as Gnucap plugins.  There are several 
different versions of Spice, with slightly different interface, 
that cannot be used interchangeably in Spice, but gnucap can use 
any of them.  In this way, output from the NGspice version of 
ADMS can be used with gnucap.