[Iverilog-devel] Use of specparams in constant expressions

[Martin W. <mai...@ma...>]

One of our users has encountered the limitation that Icarus Verilog does not 
currently support the use of specparams outside a specify block (pr3522923). 
Coincidentally, I hit the same problem recently, and have been thinking about 
it a bit. It is not entirely clear how specparams should be treated by the 
compiler. On the one hand, the standard allows a specparam to be used in any 
constant expression, on the other hand, it allows a specparam to be annotated 
with a value read from a SDF file. So, according to the standard, it is quite 
legal to write:

   specparam w = 2;

   reg [w-1:0] r;

   initial $sdf_annotate("annotate_w.sdf");

and change the value of 'w' at run time.

My practical solution to this would be to say that all constant expressions 
are evaluated at compile time and are unaffected by the $sdf_annotate task.

I tried testing this with NC-Verilog, but it doesn't support annotation of 
specparams (neatly avoiding the issue!). So do other simulators implement 
this, or was it just something dreamt up by the standards committee?

I've attached my test program, in case someone would like to try it in another 
simulator. Hopefully the SDF file is syntactically correct.

Martin