Re: [Iverilog-devel] What is a constant?

[Martin W. <mai...@ma...>]

Guy Hutchison wrote:
> Good catch by all replies, changing this to:
>    generate
>      for (g=0; g<inputs; g=g+1)
>        begin : breakout
>          wire [width-1:0] insel;
>          if (g==0)
> 	  assign insel = (rr_state[0]) ? c_data[width-1:0] : {width{1'b0}};
>          else
>            assign insel = (rr_state[g]) ? c_data>>  (g*width) :
> breakout[g-1].insel;
>        end
>    endgenerate
>    assign p_data = breakout[inputs-1].insel;
>
> Fixes the access-zero problem, as zero is the special case.
>
> As to why I am using this goofy structure, it is because building a
> parameterized mux is a little painful if you have to have constant bit
> selects, so I'm forced in to more odd constructions.

You've actually coded a priority encoder. If you really want a mux, it's a 
fairly simple change:

   generate
     for (g=0; g<inputs; g=g+1)
       begin : breakout
         wire [width-1:0] insel;
         wire [width-1:0] out;
	assign insel = {width{rr_state[g]}} & c_data[width*g +: width];
         if (g==0)
	  assign out = insel;
         else
           assign out = insel | breakout[g-1].out;
       end
   endgenerate
   assign p_data = breakout[inputs-1].out;

This should synthesise without any trouble.

If you don't need a one-hot coded select, you can always write:

   assign p_data = c_data[rr_index*width +: width];

although I've never tried synthesising a construct like this.

Martin