[Iverilog-devel] What is a constant?

[Guy H. <ghu...@gm...>]

Not sure if this is an Icarus question or an LRM question, but while
refactoring some code with generate statements I ran across this error
message:

sd_rrmux.v:151: error: Scope index expression is not constant: j

The code that caused the error was:
  generate
    for (i=0; i<inputs; i=i+1)
      begin : grid_assign
        wire [width-1:0] temp;
        assign temp = c_data >> (i*width);
        //assign rr_mux_grid[i] = c_data >> (i*width);
      end
  endgenerate
  always @*
    begin
      p_data = 0;
      p_srdy = 0;
      for (j=0; j<inputs; j=j+1)
        if (rr_state[j])
          begin
            //p_data = rr_mux_grid[j];
            p_data = grid_assign[j].temp;
            p_srdy = c_srdy[j];
          end
    end

A synthesis tool has no problem figuring out that j is constant within
the begin-end scope listed here; why is it not "constant" for picking
up a scope reference?  This also fails within a generate loop using a
genvar as the index var.