Re: [Iverilog-devel] Xilinx IP Cores

[Jared C. <jar...@gm...>]

2011/8/29 John O Battle <job...@gm...>:
> Hi
>
> I have been using Xilinx ISE from the command line and have pretty well
> figured out how to convert schematics to verilog, how to use the Xilinx
> back end etc and now I want to replace xst with iVerilog.  However when
> I try to compile my verilog files with iVerilog, I get errors like this:
>
> synth.v:46: error: Unknown module type: BUFG
> synth.v:48: error: Unknown module type: IBUFG
> synth.v:50: error: Unknown module type: BUFG
> synth.v:52: error: Unknown module type: DCM_SP
> s3e_top.v:104: error: Unknown module type: GND
>
> These errors all seem to be related to either gate core or ground.  I'm
> not really sure what is missing.  I think I need to somehow instantiate
> the missing cores but I don't know how to do that, or if its even
> possible with iverilog.  And I have no idea what is wrong with GND.
>

You just need to tell Icarus where to find these modules, which are
supplied by Xilinx in the unisims library.  In practice this means
adding '-y /opt/Xilinx/13.2/ISE_DS/ISE/verilog/src/unisims/' to the
iverilog command line (obviously putting in the correct path to the
unisims directory).  If you use any coregen cores (FIFOs, etc.) then
you also need to include the XilinxCoreLib library which is in
.../ISE/verilog/src/XilinxCoreLib.  You also need to include the
"glbl.v" module in some cases (I forget which, maybe if you use a
coregen core? I just always include it).  So that means adding
.../ISE/verilog/src/glbl.v to your list of verilog files, and maybe
adding -s glbl to your command line if you use -s <your_top_level> as
well.

Hope that helps,

Jared