Re: [Iverilog-devel] Default port values in Verilog?

[Jared C. <jar...@gm...>]

On Thu, Apr 29, 2010 at 10:18 AM, Larry Doolittle
<ldo...@re...> wrote:
> Any other ideas?
>

Default port values was added to System Verilog in 1800-2009, not sure
when or if tools will catch up. :)

Pushing the limits for fair use...

23.2.2.4 Default port values
A module declaration may specify a default value for each singular
input port. These default values shall be
constant expressions evaluated in the scope of the module where they
are defined, not in the scope of the
instantiating module.
The informal syntax to declare a default input port value in a module
is as follows:
module module_name (
...,
[ input ] [ type ] port_identifier = constant_expression,
... ) ;
Defaults can be specified only for input ports and only in ANSI style
declarations.
When the module is instantiated, input ports with default values can
be omitted from the instantiation, and
the compiler shall insert the corresponding default values. If a
connection is not specified for an input port
and the port does not have a default value, then, depending on the
connection style (ordered list, named
connections, implicit named connections, or implicit .* connections),
the port shall either be left
unconnected or result in an error, as discussed in 23.3.2.1 through 23.3.2.4.

Jared