Re: [Iverilog-devel] Code to test on other simulators (parameter selects).

[Martin W. <mai...@ma...>]

Cary R. wrote:
> I have been working on adding warnings for R-value selects
> and ran into an interesting issue in Icarus related to the
> width of a parameter. It appears that from a select
> standpoint some unsized parameter have the wrong width.
>>From looking at 1364-2005 page 36 and 37 I would have
> expected the width to be at least an integer width, but
> more if needed to contain the value. FYI here is what I'm
> getting.
> 
> parameter zero = 0; // Has infinite width, I expect integer.
> parameter mone = -1; // Has a width of 2, I expect integer.
> parameter big = 'hFFFFFFFFFFFF; // Has a width of 48.
> 
> These are run time issues, but similar issues exist for
> constant selects that are handled in the compiler.
> 
> I would like to know what other simulators return. Since
> this uses the power operator and indexed selects you will
> likely need a more modern simulator.
> 
NC-Verilog:

   parameter big = 'hffffffffffff;
                                |
ncvlog: *W,INTOVF (parm_size.v,4|31): bit overflow during conversion from text 
[2.5(IEEE)] (32 bits).

Checking the size with a bit select.
The size of a decimal 0 parameter is 32 bits.
The size of a decimal -1 parameter is 32 bits.
The size of a big decimal parameter is 32 bits.

Checking the size with an indexed part select.
The size of a decimal 0 parameter is 32 bits.
The size of a decimal -1 parameter is 32 bits.
The size of a big decimal parameter is 32 bits.

Basically unsized = 32 bits as far as NC-Verilog is concerned, even if you run 
the 64-bit version.

Martin