Re: [Iverilog-devel] The tranif1 test is not right?

[Stephen W. <st...@ic...>]

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Evan Lavelle wrote:
> Stephen Williams wrote:
> 
>> Every argument claiming that the tranif1.v test is "correct" has
>> so far relied on some hysteresis or capacitance or memory in the
>> switch for it to work.
> 
> Mine doesn't. "tranif.v" is correct because it models a real 
> transmission gate, and the simulator is responsible for applying any 
> appropriate bodge to make this so. The LRM doesn't, I think, say how 
> this bodge works, but Steven Sharp *does* say in the post I quoted (see 
> below). There's a good chance that XL and NC both do what Steve S says.

I *still* say that this replies (and models) an epsilon work of
hysteresis, but I figured out how to get the vvp run time to do
it cleanly, and without rewriting switch modeling support.

So thanks all for the robust discussion on the issue.

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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