Re: [Iverilog-devel] The tranif1 test is not right?

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
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> Cary R. wrote:
>> --- On Tue, 10/13/09, Stephen Williams <st...@ic...> wrote:
>>
>>> In fact, it's their "switch" nature that makes me think
>>> this test is wrong. Ask yourself:
>>>
>>>  - what happens when "pin" is driven 0?
>>>  - what happens when "pin" is driven 1?
>>>  - what happens when "pin" is driven X?
>>>  - what happens when "pin" is driven Z?
>>> and
>>>  - Does it make sense for the answer to any of the above to
>>>    differ depending on what happened before it?
>> 0 and 1 are real signals, X is an indeterminate real signal
>> (it's 1 or 0, we just don't know which one), but Z is special,
>> it is supposed to represent a lack of drive. I don't think
>> of this as driving Z, but more as not driving anything. In
>> that context it seems to make sense that the tranif gates
>> work as they do. If you are no longer driving a signal the
>> pulls keep it in the previous state.
> 
> But when "pin" becomes HiZ, your logic is relying on the switch
> not disconnecting until after tran resolution is done. In other
> words, one of the switches is remembering that it is closed while
> the new value is calculated. And of course then it discovers that
> the feedback is holding the switch closed.
> 
Absolutely. As I said before, "pin" doesn't become HiZ - one of the drivers of 
"pin" becomes HiZ. You can't change the state of "pin" until you have 
performed tran resolution. From section 11.6.5. of the standard:

"Switch processing shall consider all the devices in a bidirectional 
switch-connected net before it can determine the appropriate value for any 
node on the net because the inputs and outputs interact."

The only memory involved here is the current state of the network. That seems 
perfectly reasonable to me.

Martin