Re: [Iverilog-devel] The tranif1 test is not right?

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
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> 
> I've been working on some fixes to the tranifX handling in Icarus
> Verilog. I fixed a couple bugs, but now the tranif1.v test in the
> ivtest suite no longer works. I've been puzzling over it, and I now
> think that the test itself is not valid. The meat of the program
> is here:
> 
>    wire pin;
>    pullup   (weak1) (keep1);
>    pulldown (weak0) (keep0);
>    tranif1 (pin, keep1, pin);
>    tranif0 (pin, keep0, pin);
> 
> This is trying to simulate a keeper circuit, the idea being if
> the "pin" is released to HiZ, the previous value will have left
> one of the keepers enabled.
> 
> But I don't believe this should simulate properly. The tranifs
> are not drivers themselves, so if the external pin driver is
> released, "pin" will go to Z, which will close *both* gates and
> pin will stay HiZ.
> 
What you are missing is that tranifs are true (bi-directional) switches. Once 
you turn one of them on, the keeper can drive "pin" through the switch, so 
will hold "pin" at its last value until something stronger drives "pin" to 
another value.

Martin