Re: [Iverilog-devel] awkward warning

[Martin W. <mai...@ma...>]

Cary R. wrote:
> These were added to let the user know that @* is likely not
> doing what you would expect. Specifically the always block
> will run when any bit in pc changes. For this specific case
> that may not be an issues since you do not have side effects
> in the code, but it is an efficiency issues and if you have
> side effects it can make a simulation difference. FYI you
> don't need to concatenate pc[7] and pc[2:0] in the commented
> out always.
> 
> This is a major issue for array selects where this will be
> sensitive to the entire array! This was discussed on
> iverilog-devel "implicit vs explicit event tests" in the
> June time frame. We choose to follow what other simulators
> are doing, but print a warning message for any select to
> remind the user that they may not be getting what they
> expect. We could change the message if that would help.
> 
> warning: @* is sensitive to all bit changes in 'pc[7:0]'.
> 
NC-Verilog generates a warning for array selects in an @*
statement, but not for part selects. For example:

module test;

wire [7:0] Array[7:0];
reg  [7:0] Word;
reg        Bit;

always @* begin
   Word = Array[1];
   Bit = Word[1];
end

endmodule

when compiled generates the warning:

   Value = Array[1];
               |
ncvlog: *W,MRSTAR (test.v,8|14): array reference in @* implies sensitivity to 
all elements.

This would suggest they are only concerned with the efficiency
issue.

Interestingly, there's been a change of heart here. An older
version of NC-Verilog (2007 vintage) produced:

always @* begin
        |
ncvlog: *W,STARMR (test.v,7|7): @* containing memory reference not standard or 
portable.
   Word = Array[1];
              |
ncvlog: *W,MRSTAR (test.v,8|13): memory reference that was not standard in @*.

Martin