[Iverilog-devel] Genvar and wire/reg with same name

[Trevor W. <pha...@gm...>]

All,

There is a design that I have run across which appears to create a one-bit
wire/reg called "i" and in the same scope creates a genvar also called "i".
According to VCS, this is an error condition (which I would expect);
however, Icarus does not seem to have an issue with this.  Could others try
the following code example on some of the other commerical simulators that
handle generate blocks and see what they get?

Cary/Steve, is this behavior intentional or could it be a possible bug?

Thanks,
Trevor


module main;

reg i;

generate
  genvar i;
  for( i=0; i<16; i=i+1 ) begin : U
    reg a;
  end
endgenerate

initial begin
`ifdef DUMP
        $dumpfile( "generate20.vcd" );
        $dumpvars( 0, main );
`endif
        #10;
        $finish;
end

endmodule


Here is the error output from VCS:

                         Chronologic VCS (TM)
          Version Y-2006.06-SP1 -- Fri Jun 19 16:27:03 2009
               Copyright (c) 1991-2006 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

***** Warning: ACC/CLI capabilities have been enabled for the entire design.
      For faster performance enable module specific capability in pli.tab
file
Parsing design file 'generate20.v'
Warning-[IPDW] Identifier previously declared
        Second declaration for identifier 'i' ignored
        "generate20.v", 14
Top Level Modules:
       $root
       main
Error-[V2KIGFI] Generate for loop index variable must be a genvar (LRM
12.1.3.1)
        "generate20.v", 15:
        for (i = 0; (i < 16); i = (i + 1)) begin : U

1 warning
1 error
CPU time: .049 seconds to compile