Re: [Iverilog-devel] Fopen the same file twice for writeing?

[Andrei P. <pur...@gm...>]

What i was looking for was Verilog code that could write to the same
file from multiple modules. A piece of code that I found used this
modelsim "feature". Indeed this seems like a strange behaviour to me.
The only solution I can think of for this is distributing the
resulting mcd or simple fd trough ports (which is something i might
not want if I have a structural, maybe synthesizable block, with some
simulation-only children wanting to write the same file), or by the
top level assigning hierarhically the variables in the leaf nodes that
hold the file descriptors. Something that could be painful for example
in the case of generate statements.

I would like to propose an extention for icarus to support a C
freopen-like functionality to redirect stdout. What do you think about
something like this?

Andrew

On Wed, May 27, 2009 at 9:08 PM, Stephen Williams <st...@ic...> wrote:
> The behavior you get will depend on the scheduling order of the
> initial statements, and to a lesser degree on the operating system.
> Icarus Verilog uses fopen(<P>,"w") to open MCD files, and in your
> case, opening twice, the second open will truncate the first.
>
> It appears that VCS and ncsim agree with Icarus Verilog, at least
> in the broader sense. Modelsim seems to be making some special effort
> to detect that you opened the file twice and combine file descriptors,
> which may make a small bit of sense given that mcd descriptors are
> precious. But really, that strikes me as a lot of effort to support
> a bad input.
>
> I think this situation is (and should be) left unspecified. Just
> don't do that!-)