Re: [Iverilog-devel] System Verilog support

[Cary R. <cy...@ya...>]

--- On Sat, 1/10/09, sreeraj r <sre...@ya...> wrote:

> I have added -gsystem-verilog flags and submitted a patch
> in the tracker. I would like to take up that system verilog
> time literals addition task and adding assertion support ( I
> have played a lot with assertions in my projects and love to
> see that feature in Icarus.  ).

I would love to see the assertions, but it may be easier to
add the time literals first.

Before you go down that path I have a couple of System-verilog
questions. If you have a netlist that is using `timescale 1ns/1ps
what happens if you encounter a delay of 100fs? Does the
simulator need to notice this during compilation and change the
minimum time step (precision) to 100fS or is it safe to make this
a #0 delay? I'm not certain we want to just drop the delay for
this case. Hopefully the standard provides some insight.

If all this works out right you may be able to just recode
the PDelay class and the parser/lexor to handle the new
constants and then when calculate_val() is called it uses
the constants time unit vs the current time unit to scale
the constant to a system unit delay (based on the precision).

Even if the 100fS does set the minimum time step This is
just a slight modification in that you need to make the
design precision be based on this. I'm guessing that this
is not the case, but since I don't have a copy of the
standard you will need to figure out what is the correct
behavior.

If you would prefer to work on the assert statements first
let us know and we can provide some pointers on things to
consider when implementing them. I will nee to look at the
code with assert in mind before I can make too many
recommendations.

> waiting for valuable feedback ( Do you guys hang around any
> of the irc channels.)

Not normally. I'm usually busy working at my day job or fixing
bugs in Icarus and for the most part I prefer to minimize the
interruptions when doing either.