Re: [Iverilog-devel] System Verilog support

[Kevin C. <iv...@gr...>]

There isn't really a requirement that "logic" is a keyword, it's just a 
type-name. SV's type system is bad, if you want to go down the road of 
supporting it, I'd suggest giving yourself a layer of abstraction and do 
some lower level definitions from which you can derive the "logic" type 
with typedefs etc.. E.g. you can consider the base type of logic to be a 
4-value enum, and if you have a template "bit" class for handling logic 
wires you can say something like:

   enum logic_4state {lo,hi,x,z};
   typedef bit<logic_4state> logic;

The upside of that is the code is polymorphic and you can use the same 
(System)Verilog with different type definitions more easily.
 
Some other objects in Verilog are really better defined through 
templates and typedefs, e.g. a "reg" is really a driver object of type 
"logic", so if you have a template driver class you could say something 
like:

    typedef driver<logic> reg;

- which would be backward compatible and means that "reg" is just a 
type-name and not a keyword. In that vein you can then do something like:

   typedef driver<bool> breg;

- for a 2-state driver.

For mixed signal stuff I like to consider signals as having three 
orthogonal values: level, strength and certainty, so for logic I prefer 
a representation based on three bool values, so I would prefer to define 
logic as (say):

   typedef ms_bit<bool,bool,bool> logic;

- where one bool represents the level (1/0) another the strengh (driven 
or undriven), and the third if the value is known (x or not). That way I 
can get different behavior out of the same Verilog without changing the 
source, and I can more easily mix different representations within a design.

You're going to have to do all the typedef/template stuff if you want to 
support SV, so you might as well take advantage of it.

Just some thoughts,
Kev.

Stephen Williams wrote:
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> sreeraj r wrote:
>   
>> Hi all,
>>           I like to start adding system-verilog support to ICARUS.. I  just added -gsystem-verilog flag to the driver in my local copy( easy   task as Steve mentioned).While going through the   lexor_keyword.gpref..., I saw two   keywords GN_KEYWORDS_ICARUS and ..1364_2005.Which one is advisable for adding sv keywords " logic" seems to be already there with -gxtypes
>>     
>
> Neither. I'd create a new keyword category GN_KEYWORDS_1800_2005.
> SystemVerilog is IEEE 1800 and you are probably working off the -2005
> version. The compiler.h header file defines the keywork catagory mask
> bits. The definition has comments that describe what the mask is
> about, so you should see that you can select a bit and define your
> new GN_KEYWORDS_* to use that bit. Then when you add your keywords
> to the lexor_keywords.gperf file, use your bit.
>
>   
>> Can some experienced guys provide some good guidelines....( I am a n00b).I am having 6 months exp with using system verilog and with  various methodologies like ovm,vmm,etc
>>     
>
> SystemVerilog support is a *big* task. You'll be at it for a while;-)
> If you haven't already done so, make sure you've read through and
> understood the Developer Guide on the iverilog.wikia.com documentation
> wiki.
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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