Re: [Iverilog-devel] Verilog to VHDL project setup.

[Nick G. <nm...@yo...>]

Nick Gasson wrote:
> 
> I've created a clone of the repository on GitHub, with a new `vhdl' 
> branch here: http://github.com/nickg/iverilog/tree/vhdl
> 
> And the public clone URL is git://github.com/nickg/iverilog.git
> 

Just a few questions before I commit some stub code:

* The other code generators are written in C. Is it acceptable to 
develop the VHDL one in C++? I can't see any technical reason why not, 
as I've managed to get the stub code to compile and link fine.

* In the source code copyright notice I've put "Copyright (C) 2008  Nick 
Gasson (ni...@ni...)" followed by the standard GPLv2 header. Is 
this ok?

Thanks
Nick